1. Field of the Invention
The present invention relates to field programmable gate arrays (FPGAs) and methods for operating the same. More specifically, the present invention relates to a method for implementing logic functions within an FPGA by reconfiguring the FPGA.
2. Related Art
Conventional FPGAs include configurable logic blocks (CLBs) which are programmed to implement various logic functions. These logic functions are typically implemented using one or more programmable function generators within each CLB. These function generators can be programmed as read only memory (ROM) look up tables which provide output signals in response to a plurality of input signals. Each function generator can be programmed to provide an output signal which represents any function of the input signals. Thus, each function generator is capable of implementing a large number of functions. However, each function generator has a fixed number of input terminals and a fixed number of output terminals. The fixed number of input and output terminals necessarily limits the scope of the functions which can be performed by the function generator. For example, a function generator having four input terminals and one output terminal can implement a 2-to-1 multiplexer function by using two of the input terminals as input signal terminals and one of the input terminals as a control terminal. However, such a function generator has insufficient resources to implement more complex functions, such as a 3-to-1 multiplexer function or a 4-to-1 multiplexer function. Consequently, a plurality of function generators must be combined to implement these larger functions. However, the use of additional function generators undesirably increases the amount of FPGA resources required to perform a particular function.
It would therefore be desirable to have a method which expands the complexity of the functions which can be implemented by a function generator in an FPGA, thereby increasing the logic density of the FPGA.